The present invention generally relates to high speed data communications. More particularly, the present invention relates to method and circuit configured for providing pre-emphasis equalization during high speed data communications.
As the speed of high performance microprocessors increases, consistent with CMOS transistor feature size reductions, the required power supply voltage continues to shrink. For example, in high speed data communications, lower power consumption is being demanded without a loss in data transmission speed. Moreover, greater flexibility and adaptability of the data communications systems to the various communication interconnects is also being demanded. FIG. 1 shows a block diagram of a typical high speed digital communication system 100, such as may be used to interconnect between integrated circuit (IC) chips across single or multiple Printed Circuit Boards (PCB), backplanes, units, and equipment racks.
Digital communication system 100 includes a transmitter 102 and receiver 104, with transmitter 102 comprising an encoder/serializer 106 and an output buffer 110, and with receiver 104 comprising an input buffer 122 and a decoder/deserializer 126. Data is typically provided to transmitter 102 by a digital subsystem in a parallel format through a data input signal 118 along with a clock input signal 120, both of which are received in encoder/serializer 106 which generates encoded data 108. While clock input signal 120 can be externally supplied, typically, timing information for clock input signal 120 must be extracted through clock recovery on receiver 104, such as from clock output signal 130.
Encoded data 108 is transmitted by output buffer 110 comprising a driver for the transmitter, which generates an output signal 112 conforming to the established signaling requirements for this interface. Output signal 112 is transmitted along a communication channel 114 comprising a transmission medium such as traces on a printer circuit board (PCB), coaxial cable or any other like means for communication links.
Receiver 104 receives a transmitted signal 116 from transmission channel 114 which is degraded due to various limitations of the transmission channel 114, including increased attenuation at high frequencies, and which are typically caused by the skin effect of copper transmission lines and various dielectric losses. For example, the skin effect of copper is the tendency of current to concentrate flow on the outer surfaces of the copper conductor, rather than the entire conductor, resulting in a higher effective resistance. Dielectric losses can occur since the dielectric within the transmission lines and PCB traces is not a perfect lossless material, e.g., at high frequencies, some energy gets dissipated in the dielectric, resulting in a degraded signal. Input buffer 122 comprises a pre-amplifier configured to receive and amplify degraded signal 116 such that an amplified signal 124 has sufficient amplitude to drive decoder/deserializer 126, which is configured to recover the data output signal 128 and clock output signal 130.
FIG. 2 illustrates timing diagrams 202 and 204 demonstrating the effect of a bandwidth limited transmission medium on the transmitted and received waveform that is realized from communication system 100. A transmitted waveform 202, such as that of output signal 112 provided to transmission channel 114, frequently uses non-return-to-zero (NRZ) signaling, which represents a logical zero by a lower value and a logical one by a higher value. Detection of the high or low value typically includes setting a threshold halfway between those two values and making a comparison of the received value against the threshold.
A received waveform 204, such as that of transmitted signal 116 from transmission channel 114, shows the effect of bandwidth limiting on transmitted waveform 202. The bandwidth limiting is due to the frequency dependent loss in the transmission medium, which is caused by factors such as the skin effect and dielectric losses discussed above. These factors typically result in losses which are relatively greater at higher frequencies, i.e., the transmitted signal gets severely attenuated at high frequencies, thus making the channel behave, in effect, like a low pass filter.
The effect of this bandwidth limiting can be seen in that waveform 204 does not reach full amplitude in a single bit period, so the value reached depends on the number of consecutive bits that are alike. For example, a lower amplitude occurs at a high peak 206, which corresponds to a high bit after a long string of low bits, whereas a high amplitude occurs at a high peak 208, which corresponds to a long string of high bits. The difference in amplitude at peaks 206 and 208 makes it difficult for receiver 104 to distinguish the logic low and high signals, i.e., the xe2x80x9c0xe2x80x9ds and xe2x80x9c1xe2x80x9ds. Similarly, low peaks 210 and 212 both correspond to logic xe2x80x9c0xe2x80x9d, but there is a significant difference in the amplitude, depending on the string of previous bits. This effect is typically referred to as inter-symbol interference (ISI). In this manner, the maximum data rate that can be reliably transmitted in the channel 114 is very limited.
In order to address the above limitations, particularly at high frequencies, data communication systems include equalization techniques to adjust or correct the frequency characteristics of an electronic signal by restoring to the original level high frequencies of the electronic signal that have been attenuated. Equalizers can be implemented within the transmission channel, before the channel, e.g., within the transmitter, and/or after the channel, e.g., within the receiver.
FIG. 3A illustrates a block diagram showing a high speed digital communication system 300 utilizing equalization to overcome the bandwidth limitation of the transmission channel and extend the maximum rate of operation for the communication link. Similar to FIG. 1, a transmitter 302 generates a transmit signal 312. In this case, an output buffer 310 is cascaded with a transmit equalizer 313, also known as a pre-emphasis equalizer, having desirable frequency characteristics. A receiver 304 is configured to accept a degraded signal 316 similar to that of FIG. 1. Receiver 304 is cascaded with a receive equalizer 317, also known as an adaptive equalizer that adapts to the transmission channel losses. The net effect is that the combined frequency response of equalizers 313 and 317 and transmission channel 314 can be shaped to overcome the bandwidth limitation in transmission channel 314, resulting in higher overall bandwidth. In general, this shaping configuration requires equalizers 313 and 317 to provide additional gain at higher frequencies, or alternatively, to provide additional loss at lower frequencies while maintaining the high frequency gain. For the various linear buffers, amplifiers, and equalizers within communication system 300, the particular order of cascading is not important, but for practical implementations, typically one order is preferred over the other.
It is also often desirable to combine the equalization function with the buffer or amplifier function in a single element. For example, with reference to FIG. 3B, transmitter 302 can be configured with an output buffer 315 which incorporates pre-emphasis or pulse shaping equalization. Likewise, receiver 304 can be configured with an input buffer or preamplifier 323 which incorporates an equalizer filter.
The differences in performance between non-equalized and equalized transmission signals can be realized with reference to data eye diagrams of the communication systems of FIG. 1 (non-equalization) and FIG. 3(with equalization) For example, with reference to FIG. 4, the data eye of the non-equalized received signal with significant ISI is illustrated. The data eye comprises a time domain waveform showing a superposition of various transitions normalized to a multiple of the data period. FIG. 4 illustrates that both the horizontal opening, i.e., the time between zero crossing, and the vertical opening, i.e., the minimum amplitude at various time locations, are degraded due to ISI. In contrast, with reference to FIG. 5, the data eye of an appropriately equalized received signal with significantly reduced ISI is illustrated. FIG. 5 illustrates that both the horizontal opening and the vertical opening are significantly improved relative to that of FIG. 4.
As a demonstrated above, it is generally understood that output buffers of transmitters necessarily contain pre-emphasis equalization, such that a flat frequency response is obtained when the response of the buffer is combined with the response encountered in a typical electrical interconnect. Such pre-emphasis equalization is typically performed by techniques including the use of an passive analog LC filter or the use of a digital Finite Impulse Response (xe2x80x9cFIRxe2x80x9d) filter. LC filters are generally configured with only a few inductors, typically a single inductor, due to the bulky and awkward nature of such inductors. With such a simple design, LC filters are generally used for a transmission channel of a single fixed design, i.e., of a fixed length and transmission medium.
FIR filters are more commonly used for constructing pre-emphasis equalizers, particularly since FIR filters can be programmable to adapt to various types and configurations of transmission channels. FIR filters are configured with delay lines, such as through the use of flip-flops to enable delays. FIG. 6 illustrates a typical implementation of a FIR based pre-emphasis driver or buffer 600. In this FIR equalizer 600, any serial data 602 to be transmitted along with the serial clock 604 can be provided to inputs of FIR equalizer 600. Flip-flops 606, 608, and 610 are configured to generate signals 612, 614, and 616, which are one, two, and three clock cycles, respectively, delayed from serial data 602.
Signals 602, 612, 622, and 624 are multiplied by weighting coefficients C0, C1, C2, and C3 configured within buffers 618, 620, 624, and 626, respectively, whose outputs are summed by an adder 626 generating an output signal 628. This operation results in a transfer function of the form:
y(n)=C0x(n)+C1x(nxe2x88x921)+C2x(nxe2x88x922)+C3x(nxe2x88x923)
which is a classic finite impulse response filter. In practice, x(n) is a digital stream, so the weighting function is accomplished by varying the current or drive strength of the buffers, and the summing function is accomplished by current summing the outputs of the various stages. Such an architecture can also accommodate a varying number of additional stages, wherein the additional stages allow finer adjustment of the frequency response at a cost of additional complexity. A modified scheme to that of FIR filter 600 known as a tapped delay line (TDL) filter can include the delays being generated by fixed delays instead of flip-flops.
While the above equalization approaches can provide improved performance over non-equalized transmission techniques, these equalization approaches suffer from a variety of drawbacks, especially in very high speed applications,. i.e., in high speed digital links. For example, analog LC filters can be difficult to tune correctly, i.e., LC filters are not readily programmable, and severely limit the type of transmission channels that can be utilized. FIR filters are generally complicated and have high power requirements for operation. For high speed operation, the complexity of FIR filters limits the practical number of stages to about three, with the use of a single stage being very common. Additionally, FIR filters require a high speed clock for operation, which causes a significant amount of additional power to be dissipated in driving the additional flip-flops. about three, with the use of a single stage being very common. Additionally, FIR filters require a high speed clock for operation, which causes a significant amount of additional power to be dissipated in driving the additional flip-flops.
Accordingly, a need exists for an improved pre-emphasis equalization technique and circuit which is readily reprogrammable for various communication links, and does not have the limitations of the prior art with respect to power consumption and complexity.
The method and circuit according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of pulse shaping. The pre-emphasis equalization method and circuit of the present invention is compatible with standard digital output buffer configurations, so that the pre-emphasis equalization method and circuit can be incorporated with little additional complexity and power dissipation as compared to a traditional digital output buffer.
A data communication system configured with the exemplary pre-emphasis equalization circuit operates by receiving an input data stream and outputting a data stream for transmission through an interconnect or other transmission channel. In accordance with an exemplary embodiment, the data can be passed through an output buffer configured with pre-emphasis equalization, having input inverters at an input stage and output inverters at an output stage.
During operation, once an input signal to the input stage transitions, for example from a low to a high state, an input signal to the output stage is configured to a full amplitude to drive the transmission channel. Once the output stage transitions to a full amplitude, the input of the output stage is configured closer to a mid-scale amplitude. The amount of amplitude change from full scale back to mid-scale determines the amount of equalization to be provided by the output buffer to the transmission channel. In accordance with various exemplary embodiments, the pre-emphasis equalization circuit can be configured with a pulse shaping circuit, such as through a feedback arrangement or with a feedforward arrangement, for facilitating the pulse shaping functions.
In an exemplary feedback configuration, the output signal from the output stage can be sensed and provided back through a feedback path to be current summed, after a slight delay, to the input signal at the output stage. In an exemplary feedforward configuration, the input signal to the input stage can be sensed and provided through a feedforward path to be current summed, after a slight delay, to the input signal at the output stage. Thus, in either a feedback or feedforward transition, the output signal at the output stage will be reduced following a slight delay after a transition from low to high. Accordingly, after a transition, a pulse shaped output waveform can be provided by the output buffer. Similar operation of exemplary pre-emphasis equalization circuit is realized for a transition from a high state to a low state.
In addition, the pulse shaping pre-emphasis equalization can be programmable, and thus selectively configured to enable one to change the amount of pulse shaping based on the length of the transmission channel to be driven.